On Wed, 24 Feb 2021 06:11:29 +0000, Jianjun Wang <jianjun.wang@xxxxxxxxxxxx> wrote: > > Add INTx support for MediaTek Gen3 PCIe controller. > > Signed-off-by: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx> > Acked-by: Ryder Lee <ryder.lee@xxxxxxxxxxxx> > --- > drivers/pci/controller/pcie-mediatek-gen3.c | 176 ++++++++++++++++++++ > 1 file changed, 176 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index c602beb9afec..8b3b5f838b69 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -9,6 +9,9 @@ > #include <linux/clk.h> > #include <linux/delay.h> > #include <linux/iopoll.h> > +#include <linux/irq.h> > +#include <linux/irqchip/chained_irq.h> > +#include <linux/irqdomain.h> > #include <linux/kernel.h> > #include <linux/module.h> > #include <linux/pci.h> > @@ -45,6 +48,13 @@ > #define PCIE_LINK_STATUS_REG 0x154 > #define PCIE_PORT_LINKUP BIT(8) > > +#define PCIE_INT_ENABLE_REG 0x180 > +#define PCIE_INTX_SHIFT 24 > +#define PCIE_INTX_ENABLE \ > + GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) > + > +#define PCIE_INT_STATUS_REG 0x184 > + > #define PCIE_TRANS_TABLE_BASE_REG 0x800 > #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 > #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 > @@ -73,6 +83,9 @@ > * @phy: PHY controller block > * @clks: PCIe clocks > * @num_clks: PCIe clocks count for this port > + * @irq: PCIe controller interrupt number > + * @irq_lock: lock protecting IRQ register access > + * @intx_domain: legacy INTx IRQ domain > */ > struct mtk_pcie_port { > struct device *dev; > @@ -83,6 +96,10 @@ struct mtk_pcie_port { > struct phy *phy; > struct clk_bulk_data *clks; > int num_clks; > + > + int irq; > + raw_spinlock_t irq_lock; > + struct irq_domain *intx_domain; > }; > > /** > @@ -199,6 +216,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) > val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); > writel_relaxed(val, port->base + PCIE_PCI_IDS_1); > > + /* Mask all INTx interrupts */ > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); > + val &= ~PCIE_INTX_ENABLE; > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); > + > /* Assert all reset signals */ > val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); > val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; > @@ -262,6 +284,154 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) > return 0; > } > > +static int mtk_pcie_set_affinity(struct irq_data *data, > + const struct cpumask *mask, bool force) > +{ > + return -EINVAL; > +} > + > +static void mtk_intx_mask(struct irq_data *data) > +{ > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); > + unsigned long flags; > + u32 val; > + > + raw_spin_lock_irqsave(&port->irq_lock, flags); > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); > + val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT); > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > +} > + > +static void mtk_intx_unmask(struct irq_data *data) > +{ > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); > + unsigned long flags; > + u32 val; > + > + raw_spin_lock_irqsave(&port->irq_lock, flags); > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); > + val |= BIT(data->hwirq + PCIE_INTX_SHIFT); > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > +} > + > +/** > + * mtk_intx_eoi > + * @data: pointer to chip specific data > + * > + * As an emulated level IRQ, its interrupt status will remain > + * until the corresponding de-assert message is received; hence that > + * the status can only be cleared when the interrupt has been serviced. > + */ > +static void mtk_intx_eoi(struct irq_data *data) > +{ > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); > + unsigned long hwirq; > + > + hwirq = data->hwirq + PCIE_INTX_SHIFT; > + writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG); > +} > + > +static struct irq_chip mtk_intx_irq_chip = { > + .irq_enable = mtk_intx_unmask, > + .irq_disable = mtk_intx_mask, Please get rid of enable/disable. Given that you already have mask/unmask with the *same* implementation, this offers zero benefit. > + .irq_mask = mtk_intx_mask, > + .irq_unmask = mtk_intx_unmask, > + .irq_eoi = mtk_intx_eoi, > + .irq_set_affinity = mtk_pcie_set_affinity, > + .name = "INTx", > +}; [...] Other that that, this look good to me. Thanks, M. -- Without deviation from the norm, progress is not possible.