AM64 uses the same PCIe controller as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series provides an option for the pci-j721e.c driver to drive reference clock output to the connector. v1 of the patch series can be found @ [1] v2 of the patch series can be found @ [2] Changes from v2: *) Fix DT binding documentation suggested by Rob Changes from v1: *) Fixed missing initialization of "ret" variable in the error path. [1] -> http://lore.kernel.org/r/20201224115658.2795-1-kishon@xxxxxx [2] -> https://lore.kernel.org/r/20210104124103.30930-1-kishon@xxxxxx Kishon Vijay Abraham I (4): dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC PCI: j721e: Add support to provide refclk to PCIe connector .../bindings/pci/ti,j721e-pci-ep.yaml | 9 ++++---- .../bindings/pci/ti,j721e-pci-host.yaml | 19 +++++++++++------ drivers/pci/controller/cadence/pci-j721e.c | 21 ++++++++++++++++++- 3 files changed, 38 insertions(+), 11 deletions(-) -- 2.17.1
