On Wed, Feb 03, 2021 at 08:17:14PM +0000, Sergei Miroshnichenko wrote: > Hi Mika, > > On Mon, 2021-02-01 at 14:55 +0200, Mika Westerberg wrote: > > On Thu, Jan 28, 2021 at 09:39:29PM +0100, Lukas Wunner wrote: > > > On Thu, Jan 28, 2021 at 08:53:16AM -0600, Bjorn Helgaas wrote: > > > > On Fri, Dec 18, 2020 at 08:39:45PM +0300, Sergei Miroshnichenko > > > > wrote: > > > > > ... > > > > > > I intended to review and test this iteration of the series more > > > closely, but haven't been able to carve out the required time. > > > I'm adding some Thunderbolt folks to cc in the hope that they > > > can at least test the series on their development branch. > > > Getting this upstreamed should really be in the best interest > > > of Intel and other promulgators of Thunderbolt. > > > > Sure. It seems that this series was submitted in December so probably > > not applicable to the pci.git/next anymore. Anyways, I can give it a > > try > > on a TBT capable system if someone tells me what exactly to test ;-) > > Probably at least that the existing functionality still works but > > something else maybe too? > > For setups that worked fine, the only expected change is a possible > little different BAR layout (in /proc/iomem), and there should the same > quantity (or more) of BARs assigned than before. > > But if there are any problematic setups, which weren't able to arrange > new BARs, this patchset may push a bit further. Got it. > In a few days I'll provide an updated branch for our mirror of the > kernel on Github, with a complete and bumped set of patches, reducing > the steps required to test them. Sounds good, thanks!
