On Thu, 2021-01-28 at 21:39 +0100, Lukas Wunner wrote: > With Thunderbolt, this series is particularly useful if > (a) PCIe cards are hot-added with large BARs (such as GPUs) and/or > (b) the Thunderbolt daisy-chain is very long. > > Thunderbolt is essentially a cascade of nested hotplug ports, > so if more and more devices are added, it's easy to see that > the top-level hotplug port's BAR window may run out of space. > > My understanding is that Sergei's use case doesn't involve > Thunderbolt at all but rather hotplugging of GPUs and network > cards in PowerPC servers in a datacenter, which may have the > same kinds of issues. Hi Lukas, I have yet to find some Thunderbolt hardware and try it. Actually, we are hotplugging not only endpoints, but nested PCIe switches as well: those are PCIe JBOD chassis (with NVMes and SAS drives). But to deal with them we have to use an additional patchset "Movable bus numbers", that was also described during LPC2020 (including its problematic points), here is its RFC, it haven't changed much since then: https://lore.kernel.org/linux-pci/20191024172157.878735-5-s.miroshnichenko@xxxxxxxxx/T/ Can Thunderbolt have a chain of switches deep enough to have problems with bus numbers, when reserving is not the best option? Serge > I intended to review and test this iteration of the series more > closely, but haven't been able to carve out the required time. > I'm adding some Thunderbolt folks to cc in the hope that they > can at least test the series on their development branch. > Getting this upstreamed should really be in the best interest > of Intel and other promulgators of Thunderbolt. > > Thanks, > > Lukas
