On Mon, Jan 25, 2021 at 10:48:24AM +0800, Simon Xue wrote: > Document DT bindings for PCIe controller found on Rockchip SoC. > > Signed-off-by: Simon Xue <xxm@xxxxxxxxxxxxxx> > --- > .../bindings/pci/rockchip-dw-pcie.yaml | 133 ++++++++++++++++++ > 1 file changed, 133 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > new file mode 100644 > index 000000000000..24ea42203c14 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > @@ -0,0 +1,133 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: DesignWare based PCIe RC controller on Rockchip SoCs > + > +maintainers: > + - Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> > + - Simon Xue <xxm@xxxxxxxxxxxxxx> > + - Heiko Stuebner <heiko@xxxxxxxxx> > + > +description: |+ > + RK3568 SoC PCIe host controller is based on the Synopsys DesignWare > + PCIe IP and thus inherits all the common properties defined in > + designware-pcie.txt. > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +# We need a select here so we don't match all nodes with 'snps,dw-pcie' > +select: > + properties: > + compatible: > + contains: > + const: rockchip,rk3568-pcie > + required: > + - compatible > + > +properties: > + compatible: > + items: > + - const: rockchip,rk3568-pcie > + - const: snps,dw-pcie > + > + reg: > + items: > + - description: Data Bus Interface (DBI) registers > + - description: Rockchip designed configuration registers > + > + clocks: > + items: > + - description: AHB clock for PCIe master > + - description: AHB clock for PCIe slave > + - description: AHB clock for PCIe dbi > + - description: APB clock for PCIe > + - description: Auxiliary clock for PCIe > + > + clock-names: > + items: > + - const: aclk_mst > + - const: aclk_slv > + - const: aclk_dbi > + - const: pclk > + - const: aux > + > + msi-map: true > + > + num-lanes: true > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: pcie-phy > + > + power-domains: > + maxItems: 1 > + > + ranges: > + maxItems: 3 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: pipe > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - msi-map > + - num-lanes > + - phys > + - phy-names > + - power-domains > + - resets > + - reset-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie3x2: pcie@fe280000 { > + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; > + reg = <0x3 0xc0800000 0x0 0x400000>, > + <0x0 0xfe280000 0x0 0x10000>; > + reg-names = "pcie-dbi", "pcie-apb"; I believe I already said use 'dbi'. The DBI is also not 4MB. The config space goes here too, not in 'ranges'. > + bus-range = <0x20 0x2f>; > + clocks = <&cru 143>, <&cru 144>, > + <&cru 145>, <&cru 146>, > + <&cru 147>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux"; > + device_type = "pci"; > + linux,pci-domain = <2>; > + max-link-speed = <2>; > + msi-map = <0x2000 &its 0x2000 0x1000>; > + num-lanes = <2>; > + phys = <&pcie30phy>; > + phy-names = "pcie-phy"; > + power-domains = <&power 15>; > + ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000>, > + <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, > + <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; > + resets = <&cru 193>; > + reset-names = "pipe"; > + #address-cells = <3>; > + #size-cells = <2>; > + }; > + }; > +... > -- > 2.25.1 > > >
