On 12/14/20 9:38 PM, Bjorn Helgaas wrote:
On Tue, Dec 08, 2020 at 07:05:09PM +0100, Marek Vasut wrote:
On 12/8/20 5:40 PM, Bjorn Helgaas wrote:
Does this problem occur in both these cases?
1) When ASPM enters L1, and
2) When software writes PCI_PM_CTRL to put the device in D3hot?
IIUC both cases require the link to go to L1. I guess the same
software workaround applies to both cases?
Yes
If ASPM puts the Link in L1 and the device needs to DMA, how does the
Link get back to L0?
It cannot, so I would expect the DMA access would fail.
Do we use the same data abort hook? If getting
back to L0 requires help from software, it seems like that would
invalidate the L1 exit latency advertised by the devices. Wouldn't
that mean we couldn't safely enable L1 at all unless the endpoint
could tolerate unlimited exit latency?
Possibly, there could be limitations to the L1 support in some corner
cases. Does that mean the L1 support should be disabled completely ?
