On Sun, Dec 6, 2020 at 10:25 PM Florian Fainelli <f.fainelli@xxxxxxxxx> wrote:
>
> +JimQ,
>
> On 12/6/2020 12:16 PM, Krzysztof Wilczyński wrote:
> > Hello Nicolas, Florian and Florian,
> >
> > [...]
> >> -/* Configuration space read/write support */
> >> -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg)
> >> -{
> >> - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT)
> >> - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT)
> >> - | (busnr << PCIE_EXT_BUSNUM_SHIFT)
> >> - | (reg & ~3);
> >> -}
> >> -
> >> static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> >> int where)
> >> {
> >> @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> >> return PCI_SLOT(devfn) ? NULL : base + where;
> >>
> >> /* For devices, write to the config space index register */
> >> - idx = brcm_pcie_cfg_index(bus->number, devfn, 0);
> >> + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
> >> writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
> >> return base + PCIE_EXT_CFG_DATA + where;
> >> }
> > [...]
> >
> > Passing the hard-coded 0 as the "reg" argument here never actually did
> > anything, thus the 32 bit alignment was never correctly enforced.
> >
> > My question would be: should this be 32 bit aligned? It seems like the
> > intention was to perhaps make the alignment? I am sadly not intimately
> > familiar with his hardware, so I am not sure if there is something to
> > fix here or not.
Hello Krzystzof,
The value gets assigned to our config-space index register, which has
the lower two bits marked "unused". We're making sure that we are
putting zeroes there but it is most likely not necessary.
> >
> > Also, I wonder whether it would be safe to pass the offset (the "where"
> > variable) rather than hard-coded 0?
The answer is "no" for this code but "maybe" in the future -- allow me
to explain. We have two methods to access the config space:
(1) Set a designated index register to map to the base of a device's
config-space. From then we can access a 4k register set. This is the
method you see in the code and is why we set reg=0 for the index value
and then add "where" to the return address.
(2) Set our index register to the bus/slot/func/reg value, and then we
access a single data register. In this case we do set the "reg" to
the register value to set the index and then only add "where & 0x3" to
the return address.
As it turns out, (1) is not compatible with some MIPs SOCs that we
still support as they do not have the 4k data register set. So I may
be changing to (1) in a future pullreq, and if so, I will invoke
PCIE_ECAM_OFFSET(bus->number, devfn, where & ~3);
Regards,
Jim Quinlan
Broadcom STB
> >
> > Thank you for help in advance!
> >
> > Bjorn also asked the same question:
> > https://lore.kernel.org/linux-pci/20201120203428.GA272511@bjorn-Precision-5520/
> >
> > Krzysztof
> >
>
> --
> Florian
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