On Wed, 2 Dec 2020 19:46:59 +0100, Pali Rohár wrote:
> It is not HW bug or workaround for some cards but it is requirement by PCI
> Express spec. After fundamental reset is needed 100ms delay prior enabling
> link training. So update comment in code to reflect this requirement.
Applied to pci/aardvark, thanks!
[1/1] PCI: aardvark: Update comment about disabling link training
https://git.kernel.org/lpieralisi/pci/c/1d1cd163d0
Thanks,
Lorenzo
