Hello Linus Walleij,
The patch 2eeb02b28579: "PCI: faraday: Add clock handling" from May
15, 2017, leads to the following static checker warning:
drivers/pci/controller/pci-ftpci100.c:496 faraday_pci_probe()
warn: 'p->bus_clk' isn't an ERR_PTR
drivers/pci/controller/pci-ftpci100.c
443
444 /* Retrieve and enable optional clocks */
445 clk = devm_clk_get(dev, "PCLK");
446 if (IS_ERR(clk))
447 return PTR_ERR(clk);
448 ret = clk_prepare_enable(clk);
449 if (ret) {
450 dev_err(dev, "could not prepare PCLK\n");
451 return ret;
452 }
453 p->bus_clk = devm_clk_get(dev, "PCICLK");
454 if (IS_ERR(p->bus_clk))
455 return PTR_ERR(p->bus_clk);
^^^^^^^^^^^^^^^^^^^
We ensure that "p->bus_clk" is not an error pointer here.
456 ret = clk_prepare_enable(p->bus_clk);
457 if (ret) {
458 dev_err(dev, "could not prepare PCICLK\n");
459 return ret;
460 }
461
462 p->base = devm_platform_ioremap_resource(pdev, 0);
463 if (IS_ERR(p->base))
464 return PTR_ERR(p->base);
465
466 win = resource_list_first_type(&host->windows, IORESOURCE_IO);
467 if (win) {
468 io = win->res;
469 if (!faraday_res_to_memcfg(io->start - win->offset,
470 resource_size(io), &val)) {
471 /* setup I/O space size */
472 writel(val, p->base + PCI_IOSIZE);
473 } else {
474 dev_err(dev, "illegal IO mem size\n");
475 return -EINVAL;
476 }
477 }
478
479 /* Setup hostbridge */
480 val = readl(p->base + PCI_CTRL);
481 val |= PCI_COMMAND_IO;
482 val |= PCI_COMMAND_MEMORY;
483 val |= PCI_COMMAND_MASTER;
484 writel(val, p->base + PCI_CTRL);
485 /* Mask and clear all interrupts */
486 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
487 if (variant->cascaded_irq) {
488 ret = faraday_pci_setup_cascaded_irq(p);
489 if (ret) {
490 dev_err(dev, "failed to setup cascaded IRQ\n");
491 return ret;
492 }
493 }
494
495 /* Check bus clock if we can gear up to 66 MHz */
496 if (!IS_ERR(p->bus_clk)) {
^^^^^^^^^^^^^^^^^^
This check can be deleted, no?
497 unsigned long rate;
498 u32 val;
499
500 faraday_raw_pci_read_config(p, 0, 0,
501 FARADAY_PCI_STATUS_CMD, 4, &val);
502 rate = clk_get_rate(p->bus_clk);
503
504 if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
505 dev_info(dev, "33MHz bus is 66MHz capable\n");
506 max_bus_speed = PCI_SPEED_66MHz;
507 ret = clk_set_rate(p->bus_clk, 66000000);
508 if (ret)
509 dev_err(dev, "failed to set bus clock\n");
510 } else {
511 dev_info(dev, "33MHz only bus\n");
512 max_bus_speed = PCI_SPEED_33MHz;
513 }
514
515 /* Bumping the clock may fail so read back the rate */
516 rate = clk_get_rate(p->bus_clk);
517 if (rate == 33000000)
518 cur_bus_speed = PCI_SPEED_33MHz;
519 if (rate == 66000000)
520 cur_bus_speed = PCI_SPEED_66MHz;
521 }
522
523 ret = faraday_pci_parse_map_dma_ranges(p);
524 if (ret)
525 return ret;
526
527 ret = pci_scan_root_bus_bridge(host);
528 if (ret) {
529 dev_err(dev, "failed to scan host: %d\n", ret);
530 return ret;
531 }
532 p->bus = host->bus;
regards,
dan carpenter
