Stefan, On Fri, Nov 27 2020 at 10:17, Stefan Bühler wrote: > On 11/27/20 12:45 AM, Thomas Gleixner wrote: >> Can you please run this as root so the Capabilities are accessible? > > My bad, sorry. I did intend to run it as root, but should have checked > the output. Again see attached file. No problem. > 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) > Physical Slot: 1 > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 16 > NUMA node: 0 > Bus: primary=05, secondary=06, subordinate=06, sec-latency=64 > I/O behind bridge: 0000e000-0000efff > Memory behind bridge: fb400000-fb4fffff > Prefetchable memory behind bridge: fff00000-000fffff > Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- > BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 So the bridge would support MSI, but obviously the devices on the PCI side do not. > 06:00.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (prog-if 06 [16950]) > Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) > Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > Interrupt: pin A routed to IRQ 16 > NUMA node: 0 > Region 0: I/O ports at e0e0 [size=32] > Region 1: Memory at fb407000 (32-bit, non-prefetchable) [size=4K] > Region 2: I/O ports at e0c0 [size=32] > Region 3: Memory at fb406000 (32-bit, non-prefetchable) [size=4K] > Capabilities: [40] Power Management version 1 > Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0+,D1-,D2+,D3hot+,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- But that should still work because the boot interrupt quirk should not affect interrupts which are routed through the IOAPIC. Sean, any idea what's going on here? Thanks, tglx