On 23/11/2020 10:04, Daire.McNamara@xxxxxxxxxxxxx wrote:
Hi Ben, Lorenzo, We're working through a few issues with our FPGA design file to get PCIe working on our Icicle Kit board. FYI, PCIe on PolarFire SoC is not directly connected the CPU complex, instead, it is routed through the FPGA fabric. We believe we have resolved these issues around enabling/disabling clocks to FPGA fabric and memory protection layers and have been propagating the fixes through to our public facing FPGA and software repositories along with other unrelated improvements. All going well, these changes will arrive shortly.
Thanks for looking a tthis.
Ben, if you just want to use PCIe on Icicle Kit, the easiest path is probably to keep an eye on the README in our yocto-based repository @ https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp [https://avatars1.githubusercontent.com/u/51128733?s=400&v=4]<https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp> GitHub - polarfire-soc/meta-polarfire-soc-yocto-bsp: PolarFire SoC yocto Board Support Package<https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp> Microchip PolarFire SoC Yocto BSP. Microchip Polarfire-SoC Yocto 'Board Support Package' (BSP) is based on OpenEmbedded (OE). The 'Polarfire SoC Yocto BSP' layer is build on top of the RISC-V Architectural layer (meta-riscv) to provide hardware specific features and additional disk images. github.com Lorenzo, I'll post v18 of the driver, based on v5.10rc1, and roll up any fixes needed for this PFGA design file shortly. I'll also add MAINTAINERS section.
Is there any way the pcie driver could detect any of these issues and flag up user facing message saying "FPGA configuration required for PCIe" ? I will keep an eye on the yocto repo, the USB is also not working under Linux yet. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
