On 10/26/2020 9:18 PM, Rob Herring wrote:
External email: Use caution opening links or attachments
Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
resources"), the DWC driver was setting up the last memory resource
rather than the first memory resource. This doesn't matter for most
platforms which only have 1 memory resource, but it broke Tegra194 which
has a 2nd (prefetchable) memory region which requires an ATU entry. The
first region on Tegra194 relies on the default 1:1 pass-thru of outbound
transactions which doesn't need an ATU entry.
Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
Reported-by: Vidya Sagar <vidyas@xxxxxxxxxx>
Cc: Jingoo Han <jingoohan1@xxxxxxxxx>
Cc: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Signed-off-by: Rob Herring <robh@xxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 674f32db85ca..44c2a6572199 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
* ATU, so we should not program the ATU here.
*/
if (pp->bridge->child_ops == &dw_child_pcie_ops) {
- struct resource_entry *entry =
- resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
+ struct resource_entry *tmp, *entry = NULL;
+
+ /* Get last memory resource entry */
+ resource_list_for_each_entry(tmp, &pp->bridge->windows)
+ if (resource_type(tmp->res) == IORESOURCE_MEM)
+ entry = tmp;
This patch works for Tegra194 with its 'ranges' property in its current
shape. But, this still doesn't work if ATU mapping needs to be set for
both prefetchable and non-prefetchable regions. The series I pushed at
http://patchwork.ozlabs.org/project/linux-pci/list/?series=209764 works
for this condition as well.
When it comes to configuring the ATU to handle multiple memory apertures
(which is the ultimate goal), I think we need to understand the side
effects of removing I/O mapping in platforms where the number of view
ports available are not enough to have I/O mapping.
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_MEM, entry->res->start,
--
2.25.1
