On Thu, Oct 01, 2020 at 04:44:36PM -0500, Bjorn Helgaas wrote:
> From: Puranjay Mohan <puranjay12@xxxxxxxxx>
>
> Latency Tolerance Reporting (LTR) is required for the ASPM L1.2 PM
> substate. Devices with Upstream Ports (Endpoints and Switches) may support
> the optional LTR Capability. When LTR is enabled, devices transmit LTR
> messages containing Snoop and No-Snoop Latencies upstream. The L1.2
> substate may be entered if the most recent LTR values are greater than or
> equal to the LTR_L1.2_THRESHOLD from the L1 PM Substates Control 1
> register.
>
> Add a new function pci_ltr_init() which will be called from
> pci_init_capabilities() to initialize every PCIe device's LTR values.
> Add code in probe.c to evaluate LTR _DSM and save the latencies in pci_dev.
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2106,6 +2106,9 @@ static void pci_configure_ltr(struct pci_dev *dev)
> if (!pci_is_pcie(dev))
> return;
>
> + /* Read latency values (if any) from platform */
> + pci_acpi_evaluate_ltr_latency(dev);
> +
> pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
> if (!(cap & PCI_EXP_DEVCAP2_LTR))
> return;
> @@ -2400,6 +2403,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
> pci_ptm_init(dev); /* Precision Time Measurement */
> pci_aer_init(dev); /* Advanced Error Reporting */
> pci_dpc_init(dev); /* Downstream Port Containment */
> + pci_ltr_init(dev); /* Latency Tolerance Reporting */
I don't think we're doing this in quite the right order. If I
understand correctly, we have this:
pci_device_add
pci_configure_device
pci_configure_ltr
pci_acpi_evaluate_ltr_latency
acpi_evaluate_dsm(DSM_PCI_LTR_MAX_LATENCY)
pcie_capability_set_word(PCI_EXP_DEVCTL2_LTR_EN) <-- enable LTR
pci_init_capabilities
pci_ltr_init
pci_write_config_word(PCI_LTR_MAX_SNOOP_LAT) <-- set LTR msg content
So we enable LTR messages before we set the latency values in the LTR
capability. I think we need to set the values *first*.
> pcie_report_downtraining(dev);
