From: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> Rename encode_l12_threshold() to pci_lat_encode() and convert its argument from microseconds to nanoseconds so we can share it between LTR_L1.2_THRESHOLD encoding and LTR Max Snoop/No-Snoop Latency encoding. Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> --- drivers/pci/pcie/aspm.c | 39 ++++++++++++--------------------------- 1 file changed, 12 insertions(+), 27 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 253c30cc1967..beb6e2e4e5d2 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -307,6 +307,17 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); } +static void pci_lat_encode(u64 lat, u32 *scale, u32 *val) +{ + /* See PCIe r5.0, sec 7.8.3.3 and sec 6.18 */ + if (lat < 32) { *scale = 0; *val = (lat >> 0) & 0x3ff; } + else if (lat < 1024) { *scale = 1; *val = (lat >> 5) & 0x3ff; } + else if (lat < 32768) { *scale = 2; *val = (lat >> 10) & 0x3ff; } + else if (lat < 1048576) { *scale = 3; *val = (lat >> 15) & 0x3ff; } + else if (lat < 33554432) { *scale = 4; *val = (lat >> 20) & 0x3ff; } + else { *scale = 5; *val = (lat >> 25) & 0x3ff; } +} + /* Convert L0s latency encoding to ns */ static u32 calc_l0s_latency(u32 encoding) { @@ -354,32 +365,6 @@ static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val) return 0; } -static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) -{ - u32 threshold_ns = threshold_us * 1000; - - /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */ - if (threshold_ns < 32) { - *scale = 0; - *value = threshold_ns; - } else if (threshold_ns < 1024) { - *scale = 1; - *value = threshold_ns >> 5; - } else if (threshold_ns < 32768) { - *scale = 2; - *value = threshold_ns >> 10; - } else if (threshold_ns < 1048576) { - *scale = 3; - *value = threshold_ns >> 15; - } else if (threshold_ns < 33554432) { - *scale = 4; - *value = threshold_ns >> 20; - } else { - *scale = 5; - *value = threshold_ns >> 25; - } -} - struct aspm_register_info { u32 support:2; u32 enabled:2; @@ -539,7 +524,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, * least 4us. */ l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; - encode_l12_threshold(l1_2_threshold, &scale, &value); + pci_lat_encode(l1_2_threshold * 1000, &scale, &value); link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; } -- 2.25.1