Dear all,
I would like to know how a x86 CPU would behave in the following scenarios:
1) CPU is fetching data from memory, p.e.
movl eax, [esi]
Imagine that instruction causes a cache miss. Then CPU has to access main
memory in order to get that data, which it takes a few clock cycles.
While CPU is accessing bus & chipset to get data from RAM memory, a
non-mapped IRQ is raised in interrupt controller.
What happens next? Is memory fetching discarded in order to serve interrupt
service routine as soon as posible? Or, on the other way, does CPU waits
until bus access completion before serving interrupt request?
Other assumptions would be worst case posible, I mean, single core CPU,
single memory controller/single bus, no HyperThreading (no parallel CPU
threads) and calling Interrupt Service Routine causes another cache miss and
another access to system bus.
In other words, are memory read/write instructions like the one above
atomic?
2) In an embedded system I'm designing, I have a PCIe peripheral which is
accessed as memory mapped I/O. This peripheral can also generate interrupts.
I wonder what it is going to happen if I'm reading the contents of a 32 bit
register of this peripheral while it raises an IRQ. I do not want to disable
interrupts either masking this IRQ line
If chipset and PCIe bus are in use because of a read/write request from
non-irq context, and in the meantime the same PCIe peripheral raises an
interrupt, will CPU wait until completion of the read/write request
before serving Interrupt service routine, which will include another
read/write request for, p.e., Status Register of the peripheral?
Thanks very much in advance,
Ricardo
--
To unsubscribe from this list: send the line "unsubscribe linux-pci" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
