On Thu, Aug 19, 2010 at 11:51:53PM -0700, Kanoj Sarcar wrote: ... > > Now the question: is it truly guaranteed from PCI/PCIE > > and/or > > MSIX specs that the memory read/flush indeed will provide a > > strong > > interrupt reception barrier? I don't think so. The MMIO read will only guarantee that the write hit the device. An MSI could be sent to a different CPU than the one issueing the MMIO read immediately before the MMIO write is visible to the device. There is still a race condition here on the host side due to chipset issues (example Jesse already gave) and state of the CPU handling the MSI. hth, grant -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
