Re: Linux mask_msi_irq() question

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> > From: Kanoj Sarcar <kanojsarcar@xxxxxxxxx>
> > Subject: Linux mask_msi_irq() question
> > To: mitch.a.williams@xxxxxxxxx, tom.l.nguyen@xxxxxxxxx, mingo@xxxxxxxxxx
> > Cc: kanojsarcar@xxxxxxxxx
> > Date: Friday, August 13, 2010, 12:30 AM
> > Hello,
> > 
> > I have a question on msix vector masking, and was hoping
> > one of 
> > you could answer, instead of posting this question on one
> > of the lists.
> > 
> > mask_msi_irq() is doing a readback of the vector mask after
> > masking
> > an entry. I tried to dig up the history on this, and came
> > across
> > Mitch's patch from Mar 2007 against 2.6.21 where he
> > implemented the
> > readback/flush during enable/disable operations:
> > http://marc.info/?l=linux-kernel&m=117459742025894&w=2
> > 
> > In 2.6.30, I see that even mask/unmask is doing the flush
> > (arch/x86/kernel/apic/io_apic.c chip handlers use the
> > function).
> > 
> > Now the question: is it truly guaranteed from PCI/PCIE
> > and/or
> > MSIX specs that the memory read/flush indeed will provide a
> > strong
> > interrupt reception barrier? Or is it that some specific
> > devices
> > end up providing this guarantee above and beyond PCI/MSIX
> > specs?
> > 
> > Thank you for any responses.

Hi Kanoj, it's been awhile!  (Assuming you're the same Kanoj Sarcar I
knew at SGI who did some of the early Origin/Itanium/NUMA work.)

My memory of the spec is that this ordering *is* guaranteed, but that
some boxes violate it (e.g. Altix & Origin).  We jumped through some
hoops to make sure the readX functions did flush out interrupts by
adding a barriered DMA read operation to the non-relaxed variants.

Unfortunately I just put away my Mindshare book for a move this week so
I don't have it handy, maybe someone else can look up the appropriate
section and make sure.

However, there is some ordering like PIO vs MMIO that's not guaranteed
at all in the spec.  I think Ben is running into this on one of his
platforms right now.

-- 
Jesse Barnes, Intel Open Source Technology Center
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