(2010/08/11 8:14), Alexander Duyck wrote:
Kenji Kaneshige wrote:
(2010/07/31 9:58), Jeff Kirsher wrote:
From: Alexander Duyck<alexander.h.duyck@xxxxxxxxx>
+ /*
+ * both INTx and MSI are disabled after the Interrupt Disable bit
+ * is set and the Bus Master bit is cleared.
+ */
+ pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
+
+ rc = __pci_dev_reset(dev, 0);
Could you tell me why you need to program command register before reset?
"MSI enable" and "Bus Master" bits are cleared by the reset. Furthermore,
resetting the device clears the "Interrupt Disable bit", even though it
was set just before the rest. So I'm a little confused.
Thanks,
Kenji Kaneshige
The point is to prevent any pending transactions from being on the bus
while we are doing the reset. By writing only the INTX disable bit we
are disabling all interrupts from being generated, and also disabling
all DMA and MSI interrupts since the bus master enable bit is not set.
Without this change the device might be in the middle of a transaction
or sending an interrupt while we are doing the reset which may lead to
other issues after the reset.
Thank you for clarification. I understood.
Thanks,
Kenji Kaneshige
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