On Tue, 3 Aug 2010, Jesse Barnes wrote:
On Tue, 03 Aug 2010 08:30:41 -0400
Valdis.Kletnieks@xxxxxx wrote:
On Tue, 03 Aug 2010 00:36:35 -1000, Jeff Roberson said:
At least one intel chipset will occasionally negotiate a 4x link for an 8x
device in an 8x port. It is a known errata in the 5400 mch.
Can this get wrapped in some sort of 'if (chipset == MCH5400)'? There's no
sense in adding an entire second of delay going around this loop 4 times when
it's a valid config on a non-5400 chipset.
Yeah, it would be good to limit it to affected chipsets. Also, please
post it to linux-pci@xxxxxxxxxxxxxxx as well, and cc me, and we'll get
the fix in quickly.
It would be easy to add a test for the 5400 chipset. However, we've
already found a device in our testing that fails to recover if we retrain
the link.
From the pcie port driver is there an easy way to access the registers of
the connected device? It would be nice to look at the link capabilities
of the other endpoint and only retrain if they both support a wider link
and a narrower one was negotiated. I am not familiar enough with linux
pci to find that pci_dev for that child.
Thanks,
Jeff
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
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