On 06/14/2010 11:34 AM, Bjorn Helgaas wrote: > > I made the point there that an HT chain may contain multiple HT/PCI > host bridges, but you are stuck on the idea that "one HT chain == one > PCI root bus." > > I have not found the "one PCI host bridge per HT chain" requirement > in the HT spec (if you find it, please point me to it). > > If an HT chain may contain multiple HT/PCI host bridges, then it's > obvious that the HT host bridge registers read by amd_bus.c don't > contain enough information to correctly assign address space to the > PCI root buses. > A HT-to-PCI bridge appears as a PCI-to-PCI bridge (i.e. a Header Type 1 device), not as a host bridge (a Header Type 0 device). That is at least the software model as defined. -hpa -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
