(Added Jesse to CC) (2010/03/26 5:03), Alexander Duyck wrote: > While testing completion timeouts I found that hardware was not recovering. > It looks like the hot reset was never being propagated to the endpoint > devices on the bus due to the fact that we were clearing the bit too > quickly. > > The documentation I have states that we should be transmitting hot reset > TS1s for 2ms. To achieve this I have added a 2ms delay from the time we > set the secondary bus reset bit to the time we clear it. In addition I > changed the define used for the secondary bus reset bit to match the > register define that was being used. > > Signed-off-by: Alexander Duyck <alexander.h.duyck@xxxxxxxxx> Good point! Reviewed-by: Hidetoshi Seto <seto.hidetoshi@xxxxxxxxxxxxxx> Thanks, H.Seto -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
