Re: DMA reordering possible ?

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http://www.mjmwired.net/kernel/Documentation/DMA-mapping.txt

2010/1/29 yogeshwar sonawane <yogyas@xxxxxxxxx>:
> Hi all,
>
> Following questions can be of naïve nature. Kindly, help me to clarify
> the points.
> Thanks in Advance.
>
> 1) Consider a situation where a PCIe device has requested a DMA Write
> operation followed by an MSI based interrupt. Upon receiving the
> interrupt, the software will read/check the DMAed data. Now, even if
> the device is guaranteeing the ordering between the two (issuing one
> after the other), whether the I/O controller OR chipset can
> reorder/buffer them? This may result into getting interrupt before the
> data is DMAed resulting into software reading invalid data. Here data
> is residing into internal buffers of I/O controller and CPU is trying
> to read from memory. Whether such DMA reordering can happen/is allowed
> at all? Whether I/O controller can employ such intelligence(any kind
> of DMA reordering) for gaining some performance advantage? Mainly,
> focus is on high-end server class platforms having 8 or 16 cores with
> many peripherals.
>
> 2) If above situation is at all possible, then to avoid such situation
> is the responsibility of the device or the driver for that device?
> Mainly, both the components (device and driver) expected to be generic
> in nature (platform, I/O controller independent).
>
> 3) In continuation, if driver has to handle such situations, then how
> to handle such cases in Linux device driver? Any API is there for
> pending DMA flush/sync in I/O controller? I am aware of rmb(), wmb() &
> mb() which ensures ordering from CPU side i.e. slave read/writes.
> Anythings similar for DMA operations ?
>
> Kindly, update me if i am missing something.
>
> Any info,link or reference will be of great help.
>
> Thanks and Regards,
> Yogeshwar
>
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-- 
Best Regards
Lin
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