On Mon, 2009-11-30 at 13:36 -0800, Yinghai Lu wrote:
> Alex Williamson wrote:
> > Prior to 1f82de10 we always initialized the upper 32bits of the
> > prefetchable memory window, regardless of the address range used.
> > Now we only touch it for a >32bit address, which means the upper32
> > registers remain whatever the BIOS initialized them too.
> >
> > It's valid for the BIOS to set the upper32 base/limit to
> > 0xffffffff/0x00000000, which makes us program prefetchable ranges
> > like 0xffffffffabc00000 - 0x00000000abc00000
> >
> > Revert the chunk of 1f82de10 that made this conditional so we always
> > write the upper32 registers.
> >
> > Signed-off-by: Alex Williamson <alex.williamson@xxxxxx>
> > ---
> >
> > drivers/pci/setup-bus.c | 8 +++-----
> > 1 files changed, 3 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
> > index cb1a027..127d759 100644
> > --- a/drivers/pci/setup-bus.c
> > +++ b/drivers/pci/setup-bus.c
> > @@ -221,11 +221,9 @@ static void pci_setup_bridge(struct pci_bus *bus)
> > }
> > pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
> >
> > - if (pref_mem64) {
> > - /* Set the upper 32 bits of PREF base & limit. */
> > - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
> > - pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
> > - }
> > + /* Set the upper 32 bits of PREF base & limit. */
> > + pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
> > + pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
> >
> > pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
> > }
>
> when pref_mem64=0 it means that pref register is only 32 bit, we should not touch upper 32bits.
Did you read my patch description? In that case bu = lu = 0 and we
clear whatever state the BIOS left for those registers.
Alex
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