On Monday 16 November 2009 09:48:04 am Ira W. Snyder wrote:
> On Fri, Nov 13, 2009 at 06:26:52PM -0600, Bjorn Helgaas wrote:
> > If you post what you've got so far and the dmesg log, I can try to
> > help debug it.
> >
>
> Here it is, both patch and dmesg inlined. The dmesg log just keeps going
> forever after the "--- [ cut here ] ---" line.
>
> I've do not have a board plugged in behind the bridge at the moment. The
> only devices are the onboard ethernet, vga, etc. That's why the second
> host bridge has no memory behind it.
The preemption imbalance concerns me. If this patch causes that,
I'm worried that directly updating bus->resource[n] is corrupting
something.
Why didn't we find an I/O port window? The BIOS configured I/O ports
for devices, so there must be a window. You found earlier that the
I/O port aperture seemed to be described at 0xd0, so I'm curious why
we didn't find it this time.
There are two host bridges here, but the second has no devices below it.
I suppose it's possible there's some sort of "transparent" mode where
the first bridge forwards anything it sees, so the window description
at 0xd0 doesn't really matter. That would mean we couldn't support hot-
adding devices under the second bridge unless we know how to program
a real aperture in the first bridge and turn off that transparent mode.
But this is just speculation.
The two host bridges should have different buses below them. Both of
your bridges want to update resources for the bus at 0xf7883800, so
that's not going to work. If you arrange to have x86_pci_root_bus_res_quirks()
called, do you see it called twice, with a different pci_bus each time?
Bjorn
> From f5221cc24ad5fe10a6639448f26284e40e99a70f Mon Sep 17 00:00:00 2001
> From: Ira W. Snyder <iws@xxxxxxxxxxxxxxxx>
> Date: Mon, 16 Nov 2009 08:42:39 -0800
> Subject: [PATCH] PCI: read memory ranges out of Broadcom CNB20LE host bridge
>
> Read the memory ranges behind the Broadcom CNB20LE host bridge out of the
> hardware. This allows PCI hotplugging to work, since we know which memory
> range to allocate PCI BAR's from.
>
> Signed-off-by: Ira W. Snyder <iws@xxxxxxxxxxxxxxxx>
> ---
> arch/x86/pci/Makefile | 1 +
> arch/x86/pci/broadcom_bus.c | 72 +++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 73 insertions(+), 0 deletions(-)
> create mode 100644 arch/x86/pci/broadcom_bus.c
>
> diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
> index d8a0a62..f762c05 100644
> --- a/arch/x86/pci/Makefile
> +++ b/arch/x86/pci/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
>
> obj-y += common.o early.o
> obj-y += amd_bus.o
> +obj-y += broadcom_bus.o
> obj-$(CONFIG_X86_64) += intel_bus.o
>
> ifeq ($(CONFIG_PCI_DEBUG),y)
> diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c
> new file mode 100644
> index 0000000..a9406a2
> --- /dev/null
> +++ b/arch/x86/pci/broadcom_bus.c
> @@ -0,0 +1,72 @@
> +/*
> + * Read address ranges from a Broadcom CNB20LE Host Bridge
> + *
> + * Copyright (c) 2009 Ira W. Snyder <iws@xxxxxxxxxxxxxxxx>
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#define DEBUG 1
> +
> +#include <linux/delay.h>
> +#include <linux/dmi.h>
> +#include <linux/pci.h>
> +#include <linux/init.h>
> +#include <asm/pci_x86.h>
> +
> +#include "bus_numa.h"
> +
> +static int res_num = 0;
> +
> +static void __devinit cnb20le_res(struct pci_dev *dev)
> +{
> + struct pci_bus *bus = dev->bus;
> + u16 word1, word2;
> + u8 fbus, lbus;
> +
> + pci_read_config_byte(dev, 0x44, &fbus);
> + pci_read_config_byte(dev, 0x45, &lbus);
> + dev_dbg(&dev->dev, "CNB20LE: busses: %d to %d\n", fbus, lbus);
> +
> + pci_read_config_word(dev, 0xc0, &word1);
> + pci_read_config_word(dev, 0xc2, &word2);
> + if (word1 != word2) {
> + bus->resource[res_num]->start = (word1 << 16) | 0x0000;
> + bus->resource[res_num]->end = (word2 << 16) | 0xffff;
> + bus->resource[res_num]->flags = IORESOURCE_MEM;
> + dev_dbg(&dev->dev, "CNB20LE: noPF %pR\n", bus->resource[res_num]);
> + res_num++;
> + }
> +
> + pci_read_config_word(dev, 0xc4, &word1);
> + pci_read_config_word(dev, 0xc6, &word2);
> + if (word1 != word2) {
> + bus->resource[res_num]->start = (word1 << 16) | 0x0000;
> + bus->resource[res_num]->end = (word2 << 16) | 0xffff;
> + bus->resource[res_num]->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
> + dev_dbg(&dev->dev, "CNB20LE: PF %pR\n", bus->resource[res_num]);
> + res_num++;
> + }
> +
> + pci_read_config_word(dev, 0xd0, &word1);
> + pci_read_config_word(dev, 0xd2, &word2);
> + if (word1 != word2) {
> + bus->resource[res_num]->start = word1;
> + bus->resource[res_num]->end = word2;
> + bus->resource[res_num]->flags = IORESOURCE_IO;
> + dev_dbg(&dev->dev, "CNB20LE: IO %pR\n", bus->resource[res_num]);
> + res_num++;
> + }
> +
> + dev_dbg(&dev->dev, "CNB20LE: parent bus: %p number %d pri %d sec %d\n", bus, bus->number, bus->primary, bus->secondary);
> + dev_dbg(&dev->dev, "CNB20LE: parent res0: %pR\n", dev->bus->resource[0]);
> + dev_dbg(&dev->dev, "CNB20LE: parent res1: %pR\n", dev->bus->resource[1]);
> + dev_dbg(&dev->dev, "CNB20LE: parent res2: %pR\n", dev->bus->resource[2]);
> + dev_dbg(&dev->dev, "CNB20LE: parent res3: %pR\n", dev->bus->resource[3]);
> + dev_dbg(&dev->dev, "CNB20LE: parent res4: %pR\n", dev->bus->resource[4]);
> + dev_dbg(&dev->dev, "CNB20LE: parent res5: %pR\n", dev->bus->resource[5]);
> +}
> +
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, cnb20le_res);
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