On Thu, Nov 5, 2009 at 10:33 PM, Dave Airlie <airlied@xxxxxxxxx> wrote: > On Fri, Nov 6, 2009 at 6:10 AM, Alex Deucher <alexdeucher@xxxxxxxxx> wrote: >> On Thu, Nov 5, 2009 at 9:06 AM, Matthew Wilcox <matthew@xxxxxx> wrote: >>> On Thu, Nov 05, 2009 at 01:57:10PM +0100, Daniel Vetter wrote: >>>> When starting a failsafe X session and starting glxgears (which should >>>> cause plenty of interrupts to be generated), /proc/interrupts shows >>>> absolutely no MSI interrupts arriving. There are no other devices in this >>>> box using MSI interrupts. >>>> >>>> I've also tried with the lastest -linus git tree merged in, with the same >>>> effects. >>>> >>>> Booting with "pci=nomsi" works around the issue. I dunno whether this is a >>>> pci or radeon issue therefore I'm posting to both lists. lspci -v (as >>>> root) is attached below. >>> >>> That sucks, and we need to fix it. >>> >>> It's almost certainly a chipset issue, so my suspicion falls primarily >>> on this device: >>> 04:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8151 AGP Bridge (rev 14) (prog-if 00 [Normal decode]) >>> >>> We have a number of quirks to handle MSIs (both disabling their use, and >>> programming the feature in bridges that the BIOS forgot to set up) on >>> HyperTransport machines already; could you send both lspci -t and >>> lspci -vvvnn (as root) to the linux-pci list? >> >> >> While working on irq support for newer radeons I've noticed a similar >> issue on an rs780 board, but only with the integrated graphics chip >> (1002:9610). MSIs work fine on the PCIE slots and other integrated >> peripherals. When I enable MSIs on the integrated graphics chip, I >> get no MSI interrupts arriving for that device. Other MSI enabled >> devices work fine. I haven't had a chance to test any other rs780 >> systems with integrated graphics yet. >> > > Actually I suspect this is different, I'm guessing the PCIE<->AGP bridge > on the radeon card is screwing up the MSI, I suspect we shouldn't enable > MSI on AGP cards ever. As MSI interrupts are normal write transactions, they are largely transparent to bridges. Interesting to note that only more recent kernels (>~2.6.24) started setting up the MSI address register with non-8 byte alignment. It would be interesting to get the MSI address and data registers when MSIs are understood to not being received, and we can decode the pattern. Thanks, Daniel -- Daniel J Blueman -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
