On Sat, 04 Jul 2009 14:08:57 +0900 Tejun Heo <tj@xxxxxxxxxx> wrote: > Till now, CLS has been determined either by arch code or as > L1_CACHE_BYTES. Only x86 and ia64 set CLS explicitly and x86 doesn't > always get it right. On most configurations, the chance is that > firmware configures the correct value during boot. > > This patch makes pci_init() determine CLS by looking at what firmware > has configured. It scans all devices and if all non-zero values > agree, the value is used. If none is configured or there is a > disagreement, pci_dfl_cache_line_size is used. arch can set the dfl > value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or > override the actual one. > > ia64, x86 and sparc64 updated to set the default cls instead of the > actual one. > > While at it, declare pci_cache_line_size and pci_dfl_cache_line_size > in pci.h and drop private declarations from arch code. This sounds like a good improvement (though I share Ingo's concerns about platform breakage here). Can you respin the patchset against my linux-next current tree? Thanks, -- Jesse Barnes, Intel Open Source Technology Center -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
