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On Tuesday 15 September 2009, you wrote:
>
> I think you've misunderstood. The BCM5785 is a HyperTransport device,
> so it's bridging from an upstream HT bus to a downstream PCI-X bus.
> The HT bus is not running at 33MHz/32 bit ;-)
Hi Matthew,
Thanks for your response. I hope I'm not trying your patience, since I'm
pretty ignorant of pci/hypertransport bridge hardware, but I do notice a
discrepancy between the lspci output on the BCM5785 computer (the bit in
question quoted again here):
> > 00:01.0 PCI bridge: Broadcom BCM5785 [HT1000] PCI/PCI-X Bridge (prog-if
> > Capabilities: [90] PCI-X bridge device
> > Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD-
> > Freq=133MHz
> > Status: Dev=00:01.0 64bit- 133MHz- SCD- USC- SCO- SRD-
Compared to the corresponding output for a top-level pci bridge on another
amd/hypertransport computer which instead uses a amd-8131 hypertransport/pci
tunnel:
18:0a.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev
12) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Bus: primary=18, secondary=19, subordinate=19, sec-latency=64
Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [a0] PCI-X bridge device
Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD-
Freq=133MHz
Status: Dev=18:0a.0 64bit+ 133MHz+ SCD- USC- SCO- SRD-
Upstream: Capacity=14 CommitmentLimit=65535
Downstream: Capacity=2 CommitmentLimit=65535
Capabilities: [b8] HyperTransport: Interrupt Discovery and
Configuration
Capabilities: [c0] HyperTransport: Slave or Primary Interface
!!! Possibly incomplete decoding
Command: BaseUnitID=10 UnitCnt=2 MastHost- DefDir-
Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO-
<CRCErr=0
Link Config 0: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit
Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+
<CRCErr=0
Link Config 1: MLWI=8bit MLWO=8bit LWI=N/C LWO=N/C
Revision ID: 1.02
Kernel modules: shpchp
In that the amd-8131 bridge lists its own status as 64bit+ 133MHz+ where the
bcm5785 has 64bit- 133MHz-.
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