On Sat, Sep 05, 2009 at 12:00:32AM +0200, Rafael J. Wysocki wrote: > > Yes, it's presumably the case that the PME event in the bridge is just > > tied to the root bridge in the chipset. Do we know what chipset this > > hardware is? For Intel, at least, GPE behaviour is defined in the > > chipset docs. > > One box is Intel, the other one is based on an ATI (pre-AMD) chipset, but > the design is similar in that respect. GPE 0xb will be the one generated by any Intel chipset whenever the external PCI PME# goes active. 0xd is the equivalent for chipset-level devices that don't have a GPE of their own. I can't see any way that a downstream bridge could reasonably generate a GPE, so I'd bet that it's using 0xb. -- Matthew Garrett | mjg59@xxxxxxxxxxxxx -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
