Applied, after fixing up the two build errors it generated. :)
Jesse
On Wed, 1 Jul 2009 09:53:39 -0600
Matthew Wilcox <matthew@xxxxxx> wrote:
>
> You missed this patch in your recent gather-up ...
>
> ----- Forwarded message from Matthew Wilcox <matthew@xxxxxx> -----
>
> From: Matthew Wilcox <matthew@xxxxxx>
> To: linux-pci@xxxxxxxxxxxxxxx
> Subject: [PATCH] Fix IRQ swizzling for ARI-enabled devices
> List-ID: <linux-pci.vger.kernel.org>
> X-Mailing-List: linux-pci@xxxxxxxxxxxxxxx
>
>
> For many purposes, including interrupt-swizzling, devices with ARI
> enabled behave as if they have one device (number 0) and 256
> functions. This probably hasn't bitten us in practice because all ARI
> devices I've seen are also IOV devices, and IOV devices are required
> to use MSI. This isn't guaranteed, and there are legitimate reasons
> to use ARI without IOV, and hence potentially use pin-based
> interrupts.
>
> Signed-off-by: Matthew Wilcox <willy@xxxxxxxxxxxxxxx>
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 1a91bf9..407a5b9 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -1511,11 +1511,18 @@ void pci_enable_ari(struct pci_dev *dev)
> *
> * Perform INTx swizzling for a device behind one level of bridge.
> This is
> * required by section 9.1 of the PCI-to-PCI bridge specification
> for devices
> - * behind bridges on add-in cards.
> + * behind bridges on add-in cards. For devices with ARI enabled,
> the slot
> + * number is always 0 (see the Implementation Note in section
> 2.2.8.1 of
> + * the PCI Express Base Specification, Revision 2.1)
> */
> u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
> {
> - return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1;
> + if (pci_ari_enabled(dev->bus))
> + slot = 0;
> + else
> + slot = PCI_SLOT(dev->devfn));
> +
> + return (((pin - 1) + slot) % 4) + 1;
> }
>
> int
>
--
Jesse Barnes, Intel Open Source Technology Center
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