Kenji Kaneshige wrote:
Hi,
I'm sorry for the very delayed comment. May I ask you about timing
parameters?
+ pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
+ ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
+ msleep(100);
Why 100 msec here? Is this based on T_rst (1 msec)?
Yes, this is Trst.
+
+ ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
+ msleep(100);
+
I think 100 msec here is not enough for PCI/PCI-X. I think T_rhfa
is required here for PCI/PCI-X.
Yes, should be Trhfa here. PCI spec says "Device operational parameters
at frequencies under 16 MHz may be guaranteed by design rather than by
testing", so the Trhfa should be 2s (i.e. 2^25 clock / 16 MHz).
Will send a patch to update these values.
Thanks,
Yu
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