Re: FPGA PCI(e) bridge

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On Fri, Jun 19, 2009 at 09:57:48AM +0200, Thierry Reding wrote:
> So the core seems to be able to support multiple functions. On the other
> hand, 8 functions is most likely not enough for our purposes. What kind of
> limitations does PCIe have with more than eight functions?
> 
> Otherwise I'm probably stuck with either trying to find some other core that
> can run in bridge mode or having a monolithic driver to serve all logical
> devices.

OK.  The term you're looking for here is ARI (Alternate Routing-ID
Interpretation).  This allows a PCIe device to support up to 256 functions
instead of 8.  It's defined in PCIe 2.1 and is also available as an ECN
to PCIe 2.0:

http://www.pcisig.com/specifications/pciexpress/specifications/ECN-alt-rid-interpretation-070604.pdf

It's not supported by the G33 chipset, but it is supported by the X58
chipset.  To find out if your chipset supports it, run lspci -vvv (as root).
If you see a line along these lines:

                DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+

you're in luck (ARIFwd+).  If you see a line along these lines:

                DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd-

you're not (ARIFwd-).  DevCtl2 probably says ARIFwd-, but that's just
because you don't have an ARI-capable device in the slot.

ARI is a somewhat new feature, so you may well encounter bugs in the
Linux implementation.  For example, I just found a bug in the IRQ
swizzling code for ARI devices (and I'll submit a patch for it now).

I'm very interested in fixing any bugs you find in the ARI code ;-)

-- 
Matthew Wilcox				Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."
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