>> +++ b/arch/x86/pci/irq.c
>> pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
>> +#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SFI)
>> + /* For platforms only have IOAPIC, the PCI irq line is 1:1 mapped to
>> + * IOAPIC RTE entries, so we just enable RTE for the device.
>> + */
>
>The comment is a little garbled. Is the assumption here that all SFI
>platforms have an IOAPIC?
>
[[JPAN]] No, that is not the assumption. So we have the platform feature check below to see if there are IOAPIC exposed in SFI. The platform feature flags will be in another patch and posted soon.
>> + if (platform_has(X86_PLATFORM_FEATURE_IOAPIC) &&
>> + !platform_has(X86_PLATFORM_FEATURE_8259) &&
>> + !platform_has(X86_PLATFORM_FEATURE_ACPI) &&
>> + !platform_has(X86_PLATFORM_FEATURE_BIOS) &&
>> + pin) {
>> + ioapic = mp_sfi_find_ioapic(dev->irq);
>> + io_apic_set_pci_routing(ioapic,
>> + dev->irq, /* IOAPIC pin */
>> + dev->irq, /* IRQ line */
>> + 1, /* level trigger */
>> + 1); /* polarity active low */
>> + }
>> +#endif
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