Alan Cox wrote:
On Tue, 26 May 2009 22:05:08 +0900
Tejun Heo <tj@xxxxxxxxxx> wrote:
Hello,
This is regarding bko#13257.
http://bugzilla.kernel.org/show_bug.cgi?id=13257
towerlexa@xxxxxx was experiencing very slow transfer rate when using a
cardbus sata_sil SATA controller which is known to be sensitive to
cache line size setting. The reset default is zero and no one
configured it causing poor performance.
This is solvable by simply setting CLS to the correct value but who's
job is it? For non-hotplug devices, this is configured by the BIOS
(at least on PC), so for hotplug devices I think falls on the lap of
the PCI code but I'm not sure. If this is something which the
sata_sil driver should be responsible for, is there an established way
to determine the proper CLS value?
Currently its handled by pci_set_mwi() but there isn't actually a more
direct way to do this.
Yeah, I guess the assumption is that unless the device is using MWI it
doesn't care about cache line size. However, in the case of the sata_sil
controllers (and possibly other devices), the device cares about it for
other purposes (I think it's FIFO handling in this case).
Maybe we should just be setting the cache line size somewhere more
basic, like pci_set_master or something?
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