On Wed, May 13, 2009 at 02:06:30PM +0900, Hidetoshi Seto wrote:
> entry->mask_base = base;
> - entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
> - PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
> - msix_mask_irq(entry, 1);
> + entry->masked = 1;
>
Why do you add the setting of entry->masked here?
>
> + /*
> + * The states of Reserved bits[31:01] of Vector Control for MSI-X
> + * Table Entries must be 0. However, for potential future use,
> + * software must preserve the value of these reserved bits.
> + * Refer PCI spec 3.0, 6.8.2.9.
> + *
> + * Note that there are some device that refuses access to MSI-X
> + * Table Entries before MSI-X is enabled. Therefore we do it here.
> + */
I think you need to refer to PCIe 2.1 (or an ECN incorporated into it).
Some of these bits are now used.
> + list_for_each_entry(entry, &dev->msi_list, list) {
> + int vector = entry->msi_attrib.entry_nr;
> + entry->masked = readl(base + vector * PCI_MSIX_ENTRY_SIZE +
> + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
> + /* Make sure it is masked */
> + msix_mask_irq(entry, 1);
> + }
> +
> return 0;
This looks to be the same as the replacement patch I sent earlier.
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
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