Anyone working on Transaction Processing Hints?

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The PCI spec says that the interrupt mask in the MSI-X capability takes
up the bottom bit of the 32-bit Vector Control word and the other 31
bits are reserved.  The PCIe 2.1 spec defines 16 of those bits to be
used for the Steering Tag table (related to the TPH capability).

As far as I can tell, changing the Steering Tag is a rare occurrence.
The spec notes that devices should be quiesced (or merely have TPH
disabled) while the Steerring Tags are being programmed.

I would like it to be a rule that MSI-X must be disabled while Steering
Tags are reprogrammed, then re-enabled afterwards.  That way, we can
cache the value of the interrupt mask bit, and avoid an MMIO read when
masking interrupts.  The specs are very clear that the entire word must
be written at once; we can't just write the lowest byte.

Thoughts on this are greatly appreciated, especially from anyone who
has insight into how TPH and ST are going to be used by device drivers.

-- 
Matthew Wilcox				Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."
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