Hi, I posted this a week back on PCI mailing list. Probably it's a naïve question so nobody replied. To be frank still I am not clear about the answers though I have got some insight. If anyone of you could brief me, that would be great. My problem is that I don't have board to experiment yet so I don't know whether the code I have written is right or wrong, I need to wait till next month. Meanwhile, I wanted to be correct theoretically. I have gone ahead and had implementation with my basic understanding but I am not sure about couple of things Can you please help me out here: 1. I have 1 GB PCIe window starting at 0x8000000 I am not sure, how should I divide IO and memory space in that. 2. I have written access read / write functions for configuration space But I am not sure whether that is correct or not. Can you let me know some standards behind that and any code which can be looked at? 3. Our device has only one line which is mapped for legacy interrupts. How should I address the individual messages? Inherently writing map_irq function. 4. We do support msi interrupts too. Is there any reference to setup the MSI framework? 5. finally if you could point me to the PCIe linux configuration tactics, that would be great. I would attach the implementation for review soon but it would be better if anyone helps me in order to reduce the comments :) Thanks Sagar -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
