PCIe setup on Cortex A8

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hi,

I am currently setting up PCIe framework on ARM Cortex A8 based reference board. As I am doing it for the first time, I had couple of queries. The kernel version we have chosen is 2.6.24

1. How should I go for BAR assignment? I have seen that different platforms have different standards to do it. Some do it in bootloaders and very few in Linux. I am inclined to do that in bootloader as I am not going to modify any of the address space in kernel. But still wanted to know if there are implications. 
If I should do that in Kernel then if you could point to any reference source that would be helpful.

2. I see that 2.6.24 used the port bus driver for initializing the PCIE framework and specifically three different service drivers, virtual channels, aer and hotplug driver while in 2.6.28, there is a separate pcie reference code present for some of the ARM platforms like Marvell's Kirkwood. Which way should I choose? Normal PCI with PBD or 2.6.28 kind of framework and why?

3. I would be configuring the PCIe in RC mode with total five different interrupts supported:

a. MSI
b. Legacy
c. events
d. fatal errors
e. non-fatal errors

Is there any reference where I can look at to start with?

Thanks
Sagar
 
Keep your spirit young by working out problems and disagreements before they become weighty burdens that destroy happiness!!
 

--
To unsubscribe from this list: send the line "unsubscribe linux-pci" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[Index of Archives]     [DMA Engine]     [Linux Coverity]     [Linux USB]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [Greybus]

  Powered by Linux