Re: mutual exclusion locks over PCI memory

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On Mon, Feb 23, 2009 at 01:01:05PM +0530, arun c wrote:
> Hi,
...
> > I suspect you need/want at least one wmb() between those three steps
> > depending on what the remote host is polling.
> > The "VALID" field sounds redundant to me and I would drop it.
> > Updating the write_index should be enough clue for the remote side
> > to know which indexs are valid.
> 
> This is useful for me when read_index = write_index
> It will stop host to overwrite the buffer when there
> is unprocessed commands at the target side.

Keeping track of indexes is more efficient if the SW can process
multiple requests in a single pass....So I prefer it over using
a "VALID" bit.

> Target never reads write_index here.

That's what I had guessed earlier. If the Target polled the write_index
instead of VALID bit, the VALID bit wouldn't be needed. It might be nice
to have for debugging but could be ignored later.

> 
> >> Target reads commands at read_index,
> >> if and only if valid field is VALID and
> >> after processing it makes valid field
> >> INVALID and increments read_index.
> >
> > So "VALID" really means "BUSY" or "INFLIGHT".
> >
> > Don't really need share both VALID bit and head/tail indexes.
> > Avoiding sharing of the index could conserve a fair amount of CPU cycles
> > on the host side.
> 
> I really don't understand this, for me host and target
> is sharing a buffer sitting at the  PCI space.

I saw your follow up. The buffer needs to be shared.

BTW, my point is the MMIO reads are expensive for the host.
Use "get_cycles()" on the host side to see how many cycles each
MMIO read takes to access the SDRAM on the target (across the PCI bus).

hth,
grant

> The target is exposing its SDRAM over PCI and
> the buffers are local to target and over PCI to host.
> 
> In this case how to avoid sharing?
> 
> >
> >> It seems to be working for me
> >> I need to investigate further for any
> >> cache coherency issues, write now
> >> I am running with dcache off.
> >
> > This is arch specific. Host side is usually cache coherent.
> > IIRC, some embedded PPC are not.
> >
> Regards,
> Arun C
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