On Wed, Feb 18, 2009 at 01:56:43AM +0800, Yu Zhao wrote:
> Signed-off-by: Yu Zhao <yu.zhao@xxxxxxxxx>
> ---
> drivers/pci/probe.c | 6 ++--
> drivers/pci/setup-bus.c | 64 +++++++++++++++++++++++-----------------------
> include/linux/pci.h | 22 ++++++++++++++-
> 3 files changed, 55 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 4c8abd0..c0e87f6 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -296,7 +296,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
> child->resource[i] = child->parent->resource[i - 3];
> }
>
> - res = child->resource[0];
> + res = child->resource[PCI_BRIDGE_IO];
Unless PCI_BRIDGE_IO is 0, I suspect this breaks parisc PCI bus code.
drivers/parisc code assumes the hard coded numbers.
I'm looking at drivers/parisc/lba_pci.c:lba_fixup_bus().
Alpha (and most likely others) have the same assumption:
grundler@gsyprf3:/usr/src/linux-2.6/arch/alpha/kernel$ fgrep "resource[0]" *
pci.c: dev->resource[0].start = 0x170;
pci.c: dev->resource[0].end = 0x177;
pci.c: bus->resource[0] = hose->io_space;
sys_nautilus.c: bus->resource[0]->start = 0;
sys_nautilus.c: bus->resource[0]->end = 0xffff;
sys_sio.c: io_port = dev->resource[0].start;
If you need me to generate a patch for drivers/parisc, I can.
Though I think it should be trivial for you to include it with
this patch.
thanks,
grant
> pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
> pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
> base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
> @@ -319,7 +319,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
> dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
> }
>
> - res = child->resource[1];
> + res = child->resource[PCI_BRIDGE_MEM];
> pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
> pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
> base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
> @@ -332,7 +332,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
> res);
> }
>
> - res = child->resource[2];
> + res = child->resource[PCI_BRIDGE_PREF_MEM];
> pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
> pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
> base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
> diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
> index 7046089..172187e 100644
> --- a/drivers/pci/setup-bus.c
> +++ b/drivers/pci/setup-bus.c
> @@ -77,8 +77,8 @@ void pci_setup_cardbus(struct pci_bus *bus)
> dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
> pci_domain_nr(bus), bus->number);
>
> - pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
> - if (bus->resource[0]->flags & IORESOURCE_IO) {
> + pcibios_resource_to_bus(bridge, ®ion, bus->resource[PCI_CARDBUS_IO_1]);
> + if (bus->resource[PCI_CARDBUS_IO_1]->flags & IORESOURCE_IO) {
> /*
> * The IO resource is allocated a range twice as large as it
> * would normally need. This allows us to set both IO regs.
> @@ -92,8 +92,8 @@ void pci_setup_cardbus(struct pci_bus *bus)
> region.end);
> }
>
> - pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
> - if (bus->resource[1]->flags & IORESOURCE_IO) {
> + pcibios_resource_to_bus(bridge, ®ion, bus->resource[PCI_CARDBUS_IO_2]);
> + if (bus->resource[PCI_CARDBUS_IO_2]->flags & IORESOURCE_IO) {
> dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
> (unsigned long)region.start,
> (unsigned long)region.end);
> @@ -103,8 +103,8 @@ void pci_setup_cardbus(struct pci_bus *bus)
> region.end);
> }
>
> - pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
> - if (bus->resource[2]->flags & IORESOURCE_MEM) {
> + pcibios_resource_to_bus(bridge, ®ion, bus->resource[PCI_CARDBUS_PREF_MEM]);
> + if (bus->resource[PCI_CARDBUS_PREF_MEM]->flags & IORESOURCE_MEM) {
> dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n",
> (unsigned long)region.start,
> (unsigned long)region.end);
> @@ -114,8 +114,8 @@ void pci_setup_cardbus(struct pci_bus *bus)
> region.end);
> }
>
> - pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
> - if (bus->resource[3]->flags & IORESOURCE_MEM) {
> + pcibios_resource_to_bus(bridge, ®ion, bus->resource[PCI_CARDBUS_MEM]);
> + if (bus->resource[PCI_CARDBUS_MEM]->flags & IORESOURCE_MEM) {
> dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
> (unsigned long)region.start,
> (unsigned long)region.end);
> @@ -148,8 +148,8 @@ static void pci_setup_bridge(struct pci_bus *bus)
> pci_domain_nr(bus), bus->number);
>
> /* Set up the top and bottom of the PCI I/O segment for this bus. */
> - pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
> - if (bus->resource[0]->flags & IORESOURCE_IO) {
> + pcibios_resource_to_bus(bridge, ®ion, bus->resource[PCI_BRIDGE_IO]);
> + if (bus->resource[PCI_BRIDGE_IO]->flags & IORESOURCE_IO) {
> pci_read_config_dword(bridge, PCI_IO_BASE, &l);
> l &= 0xffff0000;
> l |= (region.start >> 8) & 0x00f0;
> @@ -175,8 +175,8 @@ static void pci_setup_bridge(struct pci_bus *bus)
>
> /* Set up the top and bottom of the PCI Memory segment
> for this bus. */
> - pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
> - if (bus->resource[1]->flags & IORESOURCE_MEM) {
> + pcibios_resource_to_bus(bridge, ®ion, bus->resource[PCI_BRIDGE_MEM]);
> + if (bus->resource[PCI_BRIDGE_MEM]->flags & IORESOURCE_MEM) {
> l = (region.start >> 16) & 0xfff0;
> l |= region.end & 0xfff00000;
> dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
> @@ -196,8 +196,8 @@ static void pci_setup_bridge(struct pci_bus *bus)
>
> /* Set up PREF base/limit. */
> bu = lu = 0;
> - pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
> - if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
> + pcibios_resource_to_bus(bridge, ®ion, bus->resource[PCI_BRIDGE_PREF_MEM]);
> + if (bus->resource[PCI_BRIDGE_PREF_MEM]->flags & IORESOURCE_PREFETCH) {
> l = (region.start >> 16) & 0xfff0;
> l |= region.end & 0xfff00000;
> bu = upper_32_bits(region.start);
> @@ -230,7 +230,7 @@ static void pci_bridge_check_ranges(struct pci_bus *bus)
> struct resource *b_res;
>
> b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
> - b_res[1].flags |= IORESOURCE_MEM;
> + b_res[PCI_BRIDGE_MEM].flags |= IORESOURCE_MEM;
>
> pci_read_config_word(bridge, PCI_IO_BASE, &io);
> if (!io) {
> @@ -239,7 +239,7 @@ static void pci_bridge_check_ranges(struct pci_bus *bus)
> pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
> }
> if (io)
> - b_res[0].flags |= IORESOURCE_IO;
> + b_res[PCI_BRIDGE_IO].flags |= IORESOURCE_IO;
> /* DECchip 21050 pass 2 errata: the bridge may miss an address
> disconnect boundary by one PCI data phase.
> Workaround: do not use prefetching on this device. */
> @@ -253,7 +253,7 @@ static void pci_bridge_check_ranges(struct pci_bus *bus)
> pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
> }
> if (pmem)
> - b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
> + b_res[PCI_BRIDGE_PREF_MEM].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
> }
>
> /* Helper function for sizing routines: find first available
> @@ -406,13 +406,13 @@ static void pci_bus_size_cardbus(struct pci_bus *bus)
> * Reserve some resources for CardBus. We reserve
> * a fixed amount of bus space for CardBus bridges.
> */
> - b_res[0].start = 0;
> - b_res[0].end = pci_cardbus_io_size - 1;
> - b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
> + b_res[PCI_CARDBUS_IO_1].start = 0;
> + b_res[PCI_CARDBUS_IO_1].end = pci_cardbus_io_size - 1;
> + b_res[PCI_CARDBUS_IO_1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
>
> - b_res[1].start = 0;
> - b_res[1].end = pci_cardbus_io_size - 1;
> - b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
> + b_res[PCI_CARDBUS_IO_2].start = 0;
> + b_res[PCI_CARDBUS_IO_2].end = pci_cardbus_io_size - 1;
> + b_res[PCI_CARDBUS_IO_2].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
>
> /*
> * Check whether prefetchable memory is supported
> @@ -431,17 +431,17 @@ static void pci_bus_size_cardbus(struct pci_bus *bus)
> * twice the size.
> */
> if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
> - b_res[2].start = 0;
> - b_res[2].end = pci_cardbus_mem_size - 1;
> - b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
> + b_res[PCI_CARDBUS_PREF_MEM].start = 0;
> + b_res[PCI_CARDBUS_PREF_MEM].end = pci_cardbus_mem_size - 1;
> + b_res[PCI_CARDBUS_PREF_MEM].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
>
> - b_res[3].start = 0;
> - b_res[3].end = pci_cardbus_mem_size - 1;
> - b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
> + b_res[PCI_CARDBUS_MEM].start = 0;
> + b_res[PCI_CARDBUS_MEM].end = pci_cardbus_mem_size - 1;
> + b_res[PCI_CARDBUS_MEM].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
> } else {
> - b_res[3].start = 0;
> - b_res[3].end = pci_cardbus_mem_size * 2 - 1;
> - b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
> + b_res[PCI_CARDBUS_MEM].start = 0;
> + b_res[PCI_CARDBUS_MEM].end = pci_cardbus_mem_size * 2 - 1;
> + b_res[PCI_CARDBUS_MEM].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
> }
> }
>
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index d16b913..8841c8a 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -83,6 +83,26 @@ enum pci_mmap_state {
> #define PCI_DMA_FROMDEVICE 2
> #define PCI_DMA_NONE 3
>
> +enum {
> + PCI_BRIDGE_IO,
> + PCI_BRIDGE_MEM,
> + PCI_BRIDGE_PREF_MEM,
> + PCI_BRIDGE_MAX_RESOURCE
> +};
> +
> +enum {
> + PCI_CARDBUS_IO_1,
> + PCI_CARDBUS_IO_2,
> + PCI_CARDBUS_PREF_MEM,
> + PCI_CARDBUS_MEM,
> + PCI_CARDBUS_MAX_RESOURCE
> +};
> +
> +#define PCI_BRIDGE_RESOURCE_NUM (PCI_BRIDGE_MAX_RESOURCE > \
> + PCI_CARDBUS_MAX_RESOURCE ? \
> + PCI_BRIDGE_MAX_RESOURCE : \
> + PCI_CARDBUS_MAX_RESOURCE)
> +
> /*
> * For PCI devices, the region numbers are assigned this way:
> */
> @@ -101,8 +121,6 @@ enum {
> #endif
>
> /* resources assigned to buses behind the bridge */
> -#define PCI_BRIDGE_RESOURCE_NUM 4
> -
> PCI_BRIDGE_RESOURCES,
> PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
> PCI_BRIDGE_RESOURCE_NUM - 1,
> --
> 1.5.6.4
>
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