Rolf Eike Beer wrote: > Kenji Kaneshige wrote: >> Bit 10 in Link Status register used to be defined as Training Error in >> PCI Express 1.0a specification. But it was removed by Training Error >> ECN and currently defined as undefined. So pciehp must ignore the >> value read from it. > > What happens with devices implementing only 1.0a? > Needless to say, we can no longer detect Training Error from the Training Error bit (bit 10) defined in 1.0a. But I think it has very small impact because - pciehp also checks other bits - Error condition can be detected in the subsequent operation. For example, configuration access would return error. Note that current pciehp uses Training Error bit only for error detection and it doesn't have any operation (recovery and so on) against that. So I think it is enough if we can detect errors. Thanks, Kenji Kaneshige -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
