On Sunday 14 December 2008 12:59:54 am Grant Grundler wrote: > On Fri, Dec 12, 2008 at 08:51:24AM +1100, Timothy S. Nelson wrote: > > Quick question. > > > > On Wed, 10 Dec 2008, Timothy S. Nelson wrote: > > > >> 01:00.0 VGA compatible controller: nVidia Corporation NV17 [GeForce4 MX > >> 440] (rev a3) (prog-if 00 > >> [VGA controller]) > >> Subsystem: Micro-Star International Co., Ltd. Device 8470 > >> Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > >> Stepping- SERR- FastB2B- DisINTx- > >> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- > >> <TAbort- <MAbort- >SERR- <PERR- INTx- > >> Interrupt: pin A routed to IRQ 10 > >> Region 0: Memory at f0000000 (32-bit, non-prefetchable) [disabled] > >> [size=16M] > >> Region 1: Memory at e0000000 (32-bit, prefetchable) [disabled] > >> [size=128M] > >> Region 2: Memory at e8000000 (32-bit, prefetchable) [disabled] > >> [size=512K] > >> [virtual] Expansion ROM at e8080000 [disabled] [size=128K] > > > > Under what conditions should the [disabled] in the line above disappear? > When the "MMIO enable" bit (aka "Mem-" above) is set in the Control register. > That should at least enable the "Region 0/1/2" registers. I *thought* it > would enable the Expansion ROM as well but that might not be sufficient. The low-order bit of an expansion ROM BAR is a decode-enable bit. The Mindshare book says an expansion ROM should respond only if both the Command register "Memory Space" enable bit and the Expansion ROM Enable bit are set. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
