Re: [PATCH] PCI: Add Bridge Configuration Retry bit in PCIE Control

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Updated patch with FLR capability indicated bit...

From a6478de8d190a0343580023aa93c968e6b369c51 Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang@xxxxxxxxx>
Date: Thu, 10 Jul 2008 14:39:13 +0800
Subject: [PATCH] PCI: Add Function Level Reset related bits

The bit 28 in PCI-E Capability Register indicated Function Level Reset
capability.

The bit 15 in PCI-E Control Register is Bridge Configuration Retry 
Reset and
Initiate Function Level Reset bit.

Signed-off-by: Sheng Yang <sheng.yang@xxxxxxxxx>
---
 include/linux/pci_regs.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223..b656d22 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -375,6 +375,7 @@
 #define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
 #define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value 
*/
 #define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale 
*/
+#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL		8	/* Device Control */
 #define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting 
En. */
 #define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting 
Enable */
@@ -387,6 +388,7 @@
 #define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable 
*/
 #define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
+#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration 
Retry / FLR */
 #define PCI_EXP_DEVSTA		10	/* Device Status */
 #define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
 #define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
--
1.5.6

From a6478de8d190a0343580023aa93c968e6b369c51 Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang@xxxxxxxxx>
Date: Thu, 10 Jul 2008 14:39:13 +0800
Subject: [PATCH] PCI: Add Function Level Reset related bits

The bit 28 in PCI-E Capability Register indicated Function Level Reset
capability.

The bit 15 in PCI-E Control Register is Bridge Configuration Retry Reset and
Initiate Function Level Reset bit.

Signed-off-by: Sheng Yang <sheng.yang@xxxxxxxxx>
---
 include/linux/pci_regs.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223..b656d22 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -375,6 +375,7 @@
 #define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
 #define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
 #define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
+#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL		8	/* Device Control */
 #define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
 #define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
@@ -387,6 +388,7 @@
 #define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
 #define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
+#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 #define PCI_EXP_DEVSTA		10	/* Device Status */
 #define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
 #define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
-- 
1.5.6


[Index of Archives]     [DMA Engine]     [Linux Coverity]     [Linux USB]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [Greybus]

  Powered by Linux