Change command polling frequency to 100Hz from 10Hz in order to reduce
the delay.
Note:
- 1kHz might be problematic on HZ=100 kernels.
- 1kHz might be too frequent because PCI Express specification allows
relatively long time (maximum 1 sec.) for command completion.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@xxxxxxxxxxxxxx>
---
drivers/pci/hotplug/pciehp_hpc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: 20080617/drivers/pci/hotplug/pciehp_hpc.c
===================================================================
--- 20080617.orig/drivers/pci/hotplug/pciehp_hpc.c
+++ 20080617/drivers/pci/hotplug/pciehp_hpc.c
@@ -259,8 +259,8 @@ static inline int pcie_poll_cmd(struct c
}
}
while (timeout > 1000) {
- msleep(100);
- timeout -= 100;
+ msleep(10);
+ timeout -= 10;
if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
if (slot_status & CMD_COMPLETED) {
pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
--
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