ARCH_DMA_MINALIGN was defined as 16 - this is too small - it may be
possible that two unrelated 16-byte allocations share a cache line. If one
of these allocations is written using DMA and the other is written using
cached write, the value that was written with DMA may be corrupted.
This commit changes ARCH_DMA_MINALIGN to be 128 - that's the largest
possible cache line size on parisc.
As different parisc microarchitectures have different cache line size, we
define arch_slab_minalign(), cache_line_size() and
dma_get_cache_alignment() so that the kernel may tune slab cache
parameters dynamically, based on the detected cache line size.
Signed-off-by: Mikulas Patocka <mpatocka@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
---
arch/parisc/Kconfig | 1 +
arch/parisc/include/asm/cache.h | 7 ++++++-
2 files changed, 7 insertions(+), 1 deletion(-)
Index: linux-6.10/arch/parisc/include/asm/cache.h
===================================================================
--- linux-6.10.orig/arch/parisc/include/asm/cache.h 2023-09-18 11:33:40.000000000 +0200
+++ linux-6.10/arch/parisc/include/asm/cache.h 2024-07-26 20:27:06.000000000 +0200
@@ -20,7 +20,12 @@
#define SMP_CACHE_BYTES L1_CACHE_BYTES
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+#define ARCH_DMA_MINALIGN 128
+#define ARCH_KMALLOC_MINALIGN 8
+
+#define arch_slab_minalign() ((unsigned)dcache_stride)
+#define cache_line_size() dcache_stride
+#define dma_get_cache_alignment cache_line_size
#define __read_mostly __section(".data..read_mostly")
Index: linux-6.10/arch/parisc/Kconfig
===================================================================
--- linux-6.10.orig/arch/parisc/Kconfig 2024-07-23 20:35:34.000000000 +0200
+++ linux-6.10/arch/parisc/Kconfig 2024-07-26 19:41:15.000000000 +0200
@@ -20,6 +20,7 @@ config PARISC
select ARCH_SUPPORTS_HUGETLBFS if PA20
select ARCH_SUPPORTS_MEMORY_FAILURE
select ARCH_STACKWALK
+ select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE
select HAVE_RELIABLE_STACKTRACE
select DMA_OPS
