Hi,
Please can you tell me what the relevance of this patch is to me, and
thus why I'm included in the Cc list? I have never touched this file,
not in its current path nor a previous path according to git.
Thanks.
On Mon, May 22, 2023 at 11:57:38AM +0100, Andrew Cooper wrote:
> "x86/smpboot: Support parallel startup of secondary CPUs" adds the first use
> of X2APIC_ENABLE in assembly, but older binutils don't tolerate the UL suffix.
>
> Switch to using BIT() instead.
>
> Fixes: 7e75178a0950 ("x86/smpboot: Support parallel startup of secondary CPUs")
> Reported-by: Jeffrey Hugo <quic_jhugo@xxxxxxxxxxx>
> Tested-by: Jeffrey Hugo <quic_jhugo@xxxxxxxxxxx>
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> ---
> arch/x86/include/asm/apicdef.h | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
> index bf546dfb6e58..4b125e5b3187 100644
> --- a/arch/x86/include/asm/apicdef.h
> +++ b/arch/x86/include/asm/apicdef.h
> @@ -2,6 +2,8 @@
> #ifndef _ASM_X86_APICDEF_H
> #define _ASM_X86_APICDEF_H
>
> +#include <linux/bits.h>
> +
> /*
> * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
> *
> @@ -140,8 +142,8 @@
> #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
> #define APIC_BASE_MSR 0x800
> #define APIC_X2APIC_ID_MSR 0x802
> -#define XAPIC_ENABLE (1UL << 11)
> -#define X2APIC_ENABLE (1UL << 10)
> +#define XAPIC_ENABLE BIT(11)
> +#define X2APIC_ENABLE BIT(10)
>
> #ifdef CONFIG_X86_32
> # define MAX_IO_APICS 64
>
> base-commit: 0c7ffa32dbd6b09a87fea4ad1de8b27145dfd9a6
> --
> 2.30.2
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
