Re: [PATCH] parisc: improve cach flushing in arch_sync_dma_for_cpu()

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On 5/16/23 00:28, John David Anglin wrote:
On 2023-05-15 2:39 p.m., Helge Deller wrote:
+    case DMA_BIDIRECTIONAL:
+        flush_kernel_dcache_range(addr, size);
+        purge_kernel_dcache_range_asm(addr, addr + size);
I don't think flush and purge are both needed.

I'm not sure...

Just to fully understand it. Is this short summary correct: ?
- flush_kernel_dcache_range: flush cache back to memory, but keep data in cache.
	Next read fetches the data which is still in the cache, thus the next
	read doesn't checks if data in memory has been modified in the meantime (e.g. via DMA).
- purge_kernel_dcache_range_asm: ignore currently cached data & drop any cached data in that range.
	Even if cache has dirty memory which hasn't been written back yet, drop it and don't write back.
	Next read will fetch data from memory, thus return what DMA could have stored there.

Helge




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