From: Arnd Bergmann <arnd@xxxxxxxx>
The cache management operations on DMA are different from the
other architectures:
- on DMA_TO_DEVICE, Openrisc currently invalidates the cache
after the writeback, where a simple writeback without
invalidation should be sufficient.
- on DMA_BIDIRECTIONAL, Openrisc does nothing, while most
architectures either flush before DMA, or writeback before
and invalidate after DMA. The separate invalidation for
DMA_BIDIRECTIONAL/DMA_FROM_DEVICE is only required on CPUs
that can do speculative prefetches.
Change both to have the normal set of operations.
Signed-off-by: Arnd Bergmann <arnd@xxxxxxxx>
---
arch/openrisc/kernel/dma.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index b3edbb33b621..91a00d09ffad 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -103,10 +103,10 @@ void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
switch (dir) {
case DMA_TO_DEVICE:
- /* Flush the dcache for the requested range */
+ /* Write back the dcache for the requested range */
for (cl = addr; cl < addr + size;
cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBFR, cl);
+ mtspr(SPR_DCBWR, cl);
break;
case DMA_FROM_DEVICE:
/* Invalidate the dcache for the requested range */
@@ -114,12 +114,13 @@ void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
cl += cpuinfo->dcache_block_size)
mtspr(SPR_DCBIR, cl);
break;
+ case DMA_BIDIRECTIONAL:
+ /* Flush the dcache for the requested range */
+ for (cl = addr; cl < addr + size;
+ cl += cpuinfo->dcache_block_size)
+ mtspr(SPR_DCBFR, cl);
+ break;
default:
- /*
- * NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
- * flush nor invalidate the cache here as the area will need
- * to be manually synced anyway.
- */
break;
}
}
--
2.39.2
