Re: [PATCH] parisc: Ensure page-aligned addresses in cache flush and copy functions

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On 1/28/23 00:39, Matthew Wilcox wrote:
On Fri, Jan 27, 2023 at 10:39:41PM +0100, Helge Deller wrote:
Matthew Wilcox noticed, that if ARCH_HAS_FLUSH_ON_KUNMAP is defined
(which is the case for PA-RISC), __kunmap_local() calls
kunmap_flush_on_unmap(), which may call the parisc flush functions with
a non-page-aligned address and thus the page might not be fully flushed.

To prevent similiar cases, page-align any given address in the
following parisc low-level calls:
- clear_page_asm(),
- copy_page_asm(),
- copy_user_page_asm(),
- clear_user_page_asm(),
- flush_kernel_dcache_page_asm(),
- purge_kernel_dcache_page_asm() and
- flush_kernel_icache_page()

I don't think this is the right way to go.  Imagine that we enable
large folios on architectures that don't support TRANSPARENT_HUGEPAGE
(ie PA-RISC).  Then folio_zero_range() is going to call kmap_local()
and kunmap_local() once per folio instead of once per page, and so we'll
need to flush the entire folio, not just the page.

Don't the functions mentioned above in my patch operate on standard 4k page size
for all architectures? So, if you want to flush a whole folio you will probably
not want to call those functions by iterating over the folio-memory, but call
some other function, right?
In that case flush_kernel_dcache_range_asm() is probably better suited then, as it
doesn't page-align the given address.

Helge




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