I believe this change is wrong and will reduce performance. The TLB setup for a TMPALIAS flush is local to any given CPU. So, we should only need a local TLB purge. A local TLB purge doesn't require locking to serialize PxTLB broadcasts. It is also faster than a global TLB purges Indeed, the case that might be wrong is the one that uses pdtlb. It potentially needs serialization on SMP machines. See comment in pgtable.h. Dave On 2022-09-25 2:56 a.m., Helge Deller wrote:
Limit usage of CPU-local tlb flushes in pacache.S to non-SMP machines. On 32-bit kernels this was the case already, with this patch this behaviour is used on 64-bit kernels now too. Signed-off-by: Helge Deller <deller@xxxxxx> diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S index 9a0018f1f42c..920f6ef5c3e5 100644 --- a/arch/parisc/kernel/pacache.S +++ b/arch/parisc/kernel/pacache.S @@ -539,15 +539,10 @@ ENTRY_CFI(copy_user_page_asm) /* Purge any old translations */ -#ifdef CONFIG_PA20 - pdtlb,l %r0(%r28) - pdtlb,l %r0(%r29) -#else 0: pdtlb %r0(%r28) 1: pdtlb %r0(%r29) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB) -#endif #ifdef CONFIG_64BIT /* PA8x00 CPUs can consume 2 loads or 1 store per cycle. @@ -670,12 +665,8 @@ ENTRY_CFI(clear_user_page_asm) /* Purge any old translation */ -#ifdef CONFIG_PA20 - pdtlb,l %r0(%r28) -#else 0: pdtlb %r0(%r28) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) -#endif #ifdef CONFIG_64BIT ldi (PAGE_SIZE / 128), %r1 @@ -736,12 +727,8 @@ ENTRY_CFI(flush_dcache_page_asm) /* Purge any old translation */ -#ifdef CONFIG_PA20 - pdtlb,l %r0(%r28) -#else 0: pdtlb %r0(%r28) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) -#endif 88: ldil L%dcache_stride, %r1 ldw R%dcache_stride(%r1), r31 @@ -785,12 +772,8 @@ ENTRY_CFI(purge_dcache_page_asm) /* Purge any old translation */ -#ifdef CONFIG_PA20 - pdtlb,l %r0(%r28) -#else 0: pdtlb %r0(%r28) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) -#endif 88: ldil L%dcache_stride, %r1 ldw R%dcache_stride(%r1), r31 @@ -837,17 +820,11 @@ ENTRY_CFI(flush_icache_page_asm) * have a flat address space, it's not clear which TLB will be * used. So, we purge both entries. */ -#ifdef CONFIG_PA20 - pdtlb,l %r0(%r28) -1: pitlb,l %r0(%sr4,%r28) - ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP) -#else 0: pdtlb %r0(%r28) 1: pitlb %r0(%sr4,%r28) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP) -#endif 88: ldil L%icache_stride, %r1 ldw R%icache_stride(%r1), %r31
-- John David Anglin dave.anglin@xxxxxxxx
