On 2019-10-02 10:19 a.m., Thomas Bogendoerfer wrote:
> On Sat, Sep 28, 2019 at 11:44:36PM +0200, Sven Schnelle wrote:
>> Hi List,
>>
>> i've spent quite some time this evening debugging why the Fire GL
>> doesn't work in my C8000. As reading debug output didn't give me
>> much insights, i decided to throw some Hardware at the Problem and
>> connect a Logic Analyzer to the C8000. For that i switched to an old
>> PCI Radeon 7000 which shows the same ring test failure.
> below patch (with debug print left in) got PCI radeon working for me, when
> I played with it last time. The added fdc is a real fix, while the change
> in parisc_agp_mask_memory is just a hack. The big problem there is to get
> virtual address where the memory is mapped to in user space...
>
> Thomas.
>
>
> diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
> index 15f2e7025b78..756bc4a265d9 100644
> --- a/drivers/char/agp/parisc-agp.c
> +++ b/drivers/char/agp/parisc-agp.c
> @@ -20,6 +20,7 @@
> #include <linux/agp_backend.h>
> #include <linux/log2.h>
> #include <linux/slab.h>
> +#include <linux/pagemap.h>
>
> #include <asm/parisc-device.h>
> #include <asm/ropes.h>
> @@ -162,6 +163,16 @@ parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
> info->gatt[j] =
> parisc_agp_mask_memory(agp_bridge,
> paddr, type);
> + asm volatile("fdc %%r0(%0)" : : "r" (&info->gatt[j]));
> +#if 0
> +#if 0
> + printk("i %x j %lx page %p va %lx paddr %lx gatt %lx\n",
> + i, j, mem->pages[i], __va(paddr), paddr, info->gatt[j]);
> +#else
> + printk("i %x j %lx page %p va %lx paddr %lx\n",
> + i, j, mem->pages[i], __va(paddr), paddr);
> +#endif
> +#endif
> }
> }
>
> @@ -184,7 +195,7 @@ parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
> io_pg_start = info->io_pages_per_kpage * pg_start;
> io_pg_count = info->io_pages_per_kpage * mem->page_count;
> for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
> - info->gatt[i] = agp_bridge->scratch_page;
> + // info->gatt[i] = agp_bridge->scratch_page;
> }
>
> agp_bridge->driver->tlb_flush(mem);
> @@ -195,7 +206,22 @@ static unsigned long
> parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
> int type)
> {
> - return SBA_PDIR_VALID_BIT | addr;
> +#if 1
> + u64 pa;
> + register unsigned ci; /* coherent index */
> +
> + pa = addr & IOVP_MASK;
> + mtsp(0,1);
> + asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (__va(pa)));
I believe you can remove the mtsp and just use "lci 0(%1), %0" to load the coherence index. The space
registers sr4 to sr7 are always 0 in kernel.
> +
> + pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
> +
> + pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
> +
> + return cpu_to_le64(pa);
> +#else
> + return cpu_to_le64(SBA_PDIR_VALID_BIT | addr);
> +#endif
> }
>
> static void
>
Dave
--
John David Anglin dave.anglin@xxxxxxxx
